1. Field of the Invention
This invention relates to a semiconductor device, and more particularly to a semiconductor device in which the degree of design freedom of an external terminal is increased in accordance with further increases in the number of external terminals.
2. Description of Related Art
Demands have been made in recent years for further reductions in the size and thickness of packaged semiconductor devices. In response to such demands, a packaging form known as a Wafer Level Chip Size Package (to be referred to simply as WCSP hereinafter), in which the external size of the packaging is substantially equal to the external size of the semiconductor chip, has been proposed.
A WCSP comprises a semiconductor chip. The semiconductor chip comprises a circuit element having a predetermined function and a plurality of electrode pads electrically connected to each other on the circuit element. An insulating film is formed on the surface of the semiconductor chip such that the plurality of electrode pads is exposed.
A plurality of wiring patterns connected to the exposed electrode pads is formed on the surface of the insulating film.
Electrode posts are formed on these wiring patterns. A sealing portion is then formed so as to cover the insulating film and wiring patterns and such that the top surface of the electrode posts is exposed.
A plurality of external terminals provided as solder balls used in BGA packaging, for example, is provided on the top surface of the electrode posts.
This type of WCSP has a so-called fan-in configuration in which the multiple external terminals are provided in a lattice formation, for example, in a region corresponding to a circuit-forming surface of the semiconductor chip.
As regards the mounting of the semiconductor chip comprising the external terminals in a fan-in configuration onto a printed board, Japanese Patent Application Laid-Open Publication No. 2000-208556 discloses a semiconductor device having the aim of preventing the breakage of a connecting portion between the printed board and external electrodes and comprising a semiconductor chip having electrode pads, wiring which is formed in a predetermined position on the semiconductor chip and connected to the electrode pads, external electrodes which are formed in a predetermined position on the wiring and connected to the wiring, a printed board connected to the external electrodes, and a substrate which is formed on the semiconductor chip. A resin layer is provided on the substrate for aligning the thermal expansion of the substrate and printed board, and in particular the external electrodes are provided on the resin layer.
As semiconductor devices become increasingly sophisticated, the number of external terminals formed on a single packaged semiconductor device is gradually increasing. Conventionally, such demands for increases in the number of external terminals have been met by providing constitutions in which the spacing between adjacent external terminals is narrowed. As shall be described below, however, design freedom is severely restricted by the disposal pitch and disposal positions of external terminals.
In the conventional WCSP described above, the minimum gap between adjacent external terminals is set at a concrete level of approximately 0.5 mm. In the case of a 7 mm×7 mm WCSP, the number of external terminals provided is approximately 160.
In accordance with demands for further increases in the number of external terminals on a packaged semiconductor device, it is desirable that approximately 300 external terminals be provided on a 7 mm×7 mm WCSP.
It is not technically impossible in the aforementioned WCSP to form an even larger number of external terminals on the surface of the WCSP by further narrowing the gap between adjacent external terminals.
However, it is extremely difficult to form 300 external terminals on the surface area of a 7 mm×7 mm WCSP. Moreover, if the intervals between the external terminals are narrowed, an extremely high degree of technology is required to mount the WCSP onto a mounting substrate.
For example, the intervals between the plurality of external terminals may have to be formed in alignment with the mounting pitch of the mounting substrate within a range of approximately 0.3 mm to 0.7 mm.
In a conventional packaging constitution in such a case, a semiconductor chip is connected to the substrate by means of a so-called flip chip connection and the semiconductor chip is connected to the external electrodes via the substrate. Alternatively, the substrate and semiconductor chip are connected by wire bonding and the semiconductor chip is connected to the external electrode via the substrate. Since both of these connection methods utilize a substrate, and since additional sealing material is required in accordance with the height of the wire loop, the package becomes thick. Moreover, the package becomes expensive due to the cost of the substrate. The package becomes particularly expensive when a flip chip connection is used since an expensive buildup substrate is required.
When connection is performed by means of wire bonding, the inductance of the wire part increases. An object of this invention is therefore to provide a semiconductor device having a constitution in which design freedom in the disposal pitch and disposal positions of external terminals is increased and the package itself can be made compact.